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?1 CXA2504N 40 pin ssop (plastic) e96652a82-ps sample-and-hold driver ic for lcd description the CXA2504N comprises a 6-channel sample- and-hold circuit and driver for liquid crystal display. features built-in sample-and-hold circuit for phase matching sample-and-hold circuit slew rate 280v/s (typ.) driver slew rate 190v/s (typ.) (for 300pf load capacitance) sample-and-hold circuit slew rate adjustment function driver slew rate adjustment function structure bipolar silicon monolithic ic applications liquid crystal projectors liquid crystal viewfinders small liquid crystal monitors absolute maximum ratings (ta = 25?) supply voltage v cc 117 v v cc 217 v v cc 37 v input pin voltage 1 v in 1 * 1 vcc1 v input pin voltage 2 v in 2 * 2 vcc3 v digital input pin voltage vp * 3 ?.3 to vcc3 + 0.3 v operating temperature topr ?5 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation (ta 25?) p d 1.72 * 4 w reduction rate (ta > 25?) 13.8 * 4 mw/? operating conditions supply voltage v cc 1 15.5 0.8 v v cc 2 15.5 0.8 v v cc 3 5.0 0.5 v * 1 applies to pins 4, 5, 6, 7, 8, 13, 14, 15, 16, 24, 26, 28, 34, 36 and 38. * 2 applies to pins 17 and 39. * 3 applies to pins 1, 2, 3, 18, 19, 20, 21 and 40. * 4 when mounted on 40 40mm 2 square epoxy board. sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
? 2 CXA2504N block diagram l e v e l s h i f t e r s / h s / h d r c u r r e n t s e t t i n g s / h s / h d r s / h s / h d r l e v e l s h i f t e r l e v e l s h i f t e r l e v e l s h i f t e r s / h s / h d r l e v e l s h i f t e r s / h s / h d r l e v e l s h i f t e r s / h s / h d r c u r r e n t s e t t i n g 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 1 s h 4 s h 5 s h 6 b i a s i n 5 6 i n 6 i n 5 b i a s i n 3 4 i n 4 g n d g n d g n d v c c 1 i n 3 b i a s i n 1 2 i n 2 i n 1 i s h s h 1 s h 2 s h 3 g n d v c c 2 s h 8 b i a s o u t 6 i d r b i a s o u t 5 o u t 6 b i a s o u t 4 o u t 5 o u t 4 g n d g n d s h 7 v c c 3 b i a s o u t 3 b i a s o u t 2 o u t 3 b i a s o u t 1 o u t 2 o u t 1
? 3 CXA2504N pin description pin no. symbol pin voltage equivalent circuit description 1 2 3 18 19 20 21 40 4 7 14 5 6 8 13 15 16 17 39 sh4 sh5 sh6 sh1 sh2 sh3 sh7 sh8 bias in56 bias in3 4 bias in12 in6 in5 in4 in3 in2 in1 i sh i dr ch4 sampling pulse input ch5 sampling pulse input ch6 sampling pulse input ch1 sampling pulse input ch2 sampling pulse input ch3 sampling pulse input pulse input for simultaneous resampling of ch1, 2, and 3 pulse input for simultaneous resampling of ch4, 5, and 6 inputs in5 and 6 signal center voltage inputs in3 and 4 signal center voltage inputs in1and 2 signal center voltage ch6 input * 1 ch5 input * 1 ch4 input * 1 ch3 input * 1 ch2 input * 1 ch1 input * 1 sets sample-and-hold circuit current. sample-and-hold circuit slew rate changes. sets output driver circuit current. output driver circuit slew rate changes. g n d v c c 3 2 1 4 0 2 3 1 8 1 9 2 0 1 1 0 0 2 0 0 2 0 0 v c c 1 4 7 1 4 g n d 2 0 0 2 0 5 6 1 3 1 5 1 6 v c c 1 g n d 2 0 0 1 0 0 8 0 v 3 . 0 t o 5 . 0 v 2 v 1 1 . 5 v v c c 3 g n d 2 0 0 1 0 k 3 9 1 7 2 k 1.2v 1.2v * 1 do not input a signal of 2v or less to in1 to in6.
? 4 CXA2504N pin no. symbol pin voltage equivalent circuit description 23 25 27 33 35 37 24 26 28 34 36 38 12 22 32 9 10 11 29 30 31 out1 out2 out3 out4 out5 out6 bias out1 bias out2 bias out3 bias out4 bias out5 bias out6 vcc1 vcc3 vcc2 gnd gnd gnd gnd gnd gnd ch1 output * 2 ch2 output * 2 ch3 output * 2 ch4 output * 2 ch5 output * 2 ch6 output * 2 inputs out1 signal center voltage inputs out2 signal center voltage inputs out3 signal center voltage inputs out4 signal center voltage inputs out5 signal center voltage inputs out6 signal center voltage power supply for level shifter and s/h circuit 5v system power supply output driver power supply gnd * 3 gnd * 3 gnd * 3 gnd * 3 gnd * 3 gnd * 3 g n d v c c 2 1 0 1 0 2 3 2 5 2 7 3 7 3 5 3 3 2 4 2 6 3 8 3 6 3 4 v c c 1 g n d 2 0 0 2 0 2 8 15.5v 5.0v 15.5v * 2 power consumption varies depending on the output signal when driving load capacitance. be careful not to go over the package allowable power dissipation. * 3 pins 9 to 11 and 29 to 31 must be connected to gnd potential; they must not be open.
? 5 CXA2504N electrical characteristics unless otherwise specified: vcc1 = vcc2 = 15.5v, vcc3 = 5.0v, ta = 25 c sw1 ? b, sw2 ? b, sw3 ? b, sw4 ? b, sw5 ? a, sw6 ? a, sw7 ? b, sw8 ? a, sw13 ? a, sw14 ? b, sw15 ? a, sw16 ? a, sw18 ? b, sw19 ? b, sw20 ? b, sw21 ? b, sw24 ? b, sw26 ? b, sw28 ? b, sw34 ? b, sw36 ? b, sw38 ? b, sw40 ? b v 1 = 5v, v 2 = 5v, v 3 = 5v, v 18 = 5v, v 19 = 5v, v 20 = 5v, v 21 = 5v, v 40 = 5v, cl = 300pf no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 current consumption (1) current consumption (2) current consumption (3) sh4 ??pin current sh4 ??pin current sh5 ??pin current sh5 ??pin current sh6 ??pin current sh6 ??pin current bias in56 pin current in6 pin current in5 pin current bias in34 pin current in4 pin current in3 pin current bias in12 pin current in2 pin current in1 pin current sh1 ??pin current sh1 ??pin current sh2 ??pin current sh2 ??pin current sh3 ??pin current sh3 ??pin current sh7 ??pin current sh7 ??pin current bias out1 pin current bias out2 pin current bias out3 pin current bias out4 pin current bias out5 pin current sw5 ? b, sw6 ? b, sw8 ? b, sw13 ? b, sw15 ? b, sw16 ? b, v 1 = v 6 = v 8 = v 13 = v 15 = v 16 = 7v sw1 ? b, v 1 = 5v sw1 ? b, v 1 = 0v sw2 ? b, v 2 = 5v sw2 ? b, v 2 = 0v sw3 ? b, v 3 = 5v sw3 ? b, v 3 = 0v sw4 ? a, v 4 = 7v sw5 ? b, v 5 = 7v sw6 ? b, v 6 = 7v sw7 ? a, v 7 = 7v sw8 ? b, v 8 = 7v sw13 ? b, v 13 = 7v sw14 ? a, v 14 = 7v sw15 ? b, v 15 = 7v sw16 ? b, v 16 = 7v sw18 ? b, v 18 = 5v sw18 ? b, v 18 = 0v sw19 ? b, v 19 = 5v sw19 ? b, v 19 = 0v sw20 ? b, v 20 = 5v sw20 ? b, v 20 = 0v sw21 ? b, v 21 = 5v sw21 ? b, v 21 = 0v sw24 ? a, v 24 = 7v sw26 ? a, v 26 = 7v sw28 ? a, v 28 = 7v sw34 ? a, v 34 = 7v sw36 ? a, v 36 = 7v ?.1 ?2 ?.1 ?2 ?.1 ?2 ?.2 ?.2 ?.2 ?.1 ?2 ?.1 ?2 ?.1 ?2 ?.1 ?2 ?.2 ?.2 ?.2 ?.2 ?.2 17 8 12 0 ?.0 0 ?.0 0 ?.0 0 0.5 0.5 0 0.5 0.5 0 0.5 0.5 0 ? 0 ? 0 ? 0 ? 0 0 0 0 0 24 14 17 0.1 0.1 0.1 0.2 2.0 2.0 0.2 2.0 2.0 0.2 2.0 2.0 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 0.2 ma ma ma a a a a a a a a a a a a a a a a a a a a a a a a a a a a item symbol min. typ. max. unit icc1 icc2 icc3 i 1h i 1l i 2h i 2l i 3h i 3l i 4 i 5 i 6 i 7 i 8 i 13 i 14 i 15 i 16 i 18h i 18l i 19h i 19l i 20h i 20l i 21h i 21l i 24 i 26 i 28 i 34 i 36 measurement conditions
? 6 CXA2504N no. 32 33 34 35 36 37 38 39 40 41 bias out6 pin current sh8 ??pin current sh8 ??pin current i sh pin voltage i dr pin voltage output potential difference between channels gain difference between channels input/output gain sample-and-hold slew rate (1) sample-and-hold slew rate (2) sw38 ? a, v 38 = 7v sw40 ? b, v 40 = 5v sw40 ? b, v 40 = 0v set sw5 ? b, sw6 ? b, sw8 ? b, sw13 ? b, sw15 ? b, sw16 ? b, v 5 = v 6 = v 8 = v 13 = v 15 = v 16 = 2v, 7v, 11.5v. measure output dc voltage for tp23, tp25, tp27, tp33, tp35 and tp37 relative to each input dc voltage. d v o = max (output voltage ?input voltage) ? min (output voltage ?input voltage) set sw4 ? a, sw5 ? b, sw6 ? b, sw7 ? a, sw8 ? b, sw13 ? b, sw14 ? a, sw15 ? b, sw16 ? b, sw24 ? a, sw26 ? b, sw28 ? b, sw34 ? b, sw36 ? b, sw38 ? b, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, v 5 = v 6 = v 8 = v 13 = v 15 = v 16 = 2v, 11.5v. measure output dc voltage for tp23, tp25, tp27, tp33, tp35 and tp37 relative to each input dc voltage. ? vdmax = max (output voltage (11.5v input) ?output voltage (2.0v input)) ? vdmin = min (output voltage (11.5v input) ?output voltage (2.0v input)) and, calculate the difference between channels of its voltage difference. ? vd = ? vdmax ? ? vdmin set sw4 ? a, sw7 ? a, sw14 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v. input sg1 to (in1) to (in6) and measure gain between input and output for tp23, tp25, tp27, tp33, tp35 and tp37 (refer to output waveforms (1)). set sw1 ? a, sw2 ? a, sw3 ? a, sw4 ? a, sw7 ? a, sw14 ? a, sw18 ? a, sw19 ? a, sw20 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh1) to (sh6) = sg4. input sg2 and sg3 to (in1) to (in6) and measure output waveform (2) v for tp23, tp25, tp27, tp33, tp35 and tp37. r tsh1 = (v/ s) set sw4 ? a, sw7 ? a, sw14 ? a, sw21 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, sw40 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh7) = (sh8) = sg4. input sg2 and sg3 to (in1) to (in6) and measure output waveform (2) v for tp23, tp25, tp27, tp33, tp35 and tp37. r tsh2 = (v/ s) ?.2 ?.1 ?2 ?.5 220 220 0 0 ? 1.2 1.2 ?.1 280 280 0.2 0.1 25 25 a a a v v mv mw db v/ s v/ s item symbol min. typ. max. unit i 38 i 40h i 40l v 17 v 39 d v o d vd g io r tsh1 r tsh2 measurement conditions v 15 10 3 v 15 10 3
? 7 CXA2504N no. 42 43 44 45 46 47 sample-and-hold droop rate (1) sample-and-hold droop rate (2) driver slew rate sh7, sh8 ? output propagation delay time input ? output propagation delay time input dynamic range set sw1 ? a, sw2 ? a, sw3 ? a, sw4 ? a, sw5 ? b, sw6 ? b, sw7 ? a, sw8 ? b, sw13 ? b, sw14 ? a , sw15 ? b, sw16 ? b, sw18 ? a, sw19 ? a, sw20 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh1) to (sh6) = sg5, v 5 = v 6 = v 8 = v 13 = v 15 = v 16 = 2v, 7v, 11.5v. measure output waveform (3) v for tp23, tp25, tp27, tp33, tp35 and tp37 relative to each input dc. r d1 = (mv/ s) set sw4 ? a, sw5 ? b, sw6 ? b, sw7 ? a, sw8 ? b, sw13 ? b, sw14 ? a, sw15 ? b, sw16 ? b, sw21 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, sw40 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh7) = (sh8) = sg5, v 5 = v 6 = v 8 = v 13 = v 15 = v 16 = 2v, 7v, 11.5v. measure output waveform (3) v for tp23, tp25, tp27, tp33, tp35 and tp37 relative to each input dc. r d2 = (mv/ s) set sw4 ? a, sw7 ? a, sw14 ? a, sw21 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, sw40 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh7) = (sh8) = sg8. input sg6 and sg7 to (in1) to (in6) and measure output waveform (4) t and v for tp23, tp25, tp27, tp33, tp35 and tp37. r tdr = (v/ s) set sw4 ? a, sw7 ? a, sw14 ? a, sw21 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, sw40 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, (sh7) = (sh8) = sg8. input sg6 and sg7 to (in1) to (in6) and for each of the four conditions for input signal rise and fall, measure output waveform (4) t p for tp23, tp25, tp27, tp33, tp35 and tp37. set sw4 ? a, sw7 ? a, sw14 ? a, sw24 ? a, sw26 ? a, sw28 ? a, sw34 ? a, sw36 ? a, sw38 ? a, v 4 = v 7 = v 14 = v 24 = v 26 = v 28 = v 34 = v 36 = v 38 = 7v, cl = 0pf. input sg9 and sg10 to (in1) to (in6) and for each of the four conditions for input signal rise and fall, measure output waveform (5) t d for tp23, tp25, tp27, tp33, tp35 and tp37. 130 13 7 2.0 190 17 10 40 40 21 13 11.5 mv/ s mv/ s v/ s ns ns v item symbol min. typ. max. unit r d1 r d2 r tdr t plh (h) t phl (h) t plh (l) t phl (l) t dlh (h) t dhl (h) t dlh (l) t dhl (l) v din measurement conditions v 0.8 t v 10 v 10
? 8 CXA2504N 1 1 . 5 v 2 v a p p r o x . 1 1 . 5 v a p p r o x . 2 v m e a s u r e m e n t l e v e l 3 0 s 3 0 s i n p u t w a v e f o r m s g 1 o u t p u t w a v e f o r m ( 1 ) 1 1 . 5 v 6 . 5 v i n p u t s i g n a l s g 2 7 v 2 v i n p u t s i g n a l s g 3 5 v 0 i n p u t s i g n a l s g 4 7 5 n s 1 5 n s m e a s u r e m e n t l e v e l v m e a s u r e m e n t l e v e l v o u t p u t w a v e f o r m ( 2 ) s a m p l e - a n d - h o l d s l e w r a t e = v 1 5 1 0 3 s g 2 a n d s g 3 m u s t c h a n g e c o m p l e t e l y w i t h i n s g 4 l i n t e r v a l .
? 9 CXA2504N 5 v 0 v m e a s u r e m e n t l e v e l v 2 0 s 2 0 s i n p u t s i g n a l s g 5 o u t p u t w a v e f o r m ( 3 ) 1 1 . 5 v 8 v i n p u t s i g n a l s g 6 5 v 0 v i n p u t s i g n a l s g 8 7 5 n s 1 5 n s 1 0 s d r o o p r a t e = v 1 0 ( m v / s ) 5 . 5 v 2 v i n p u t s i g n a l s g 7 5 0 % 5 0 % m e a s u r e m e n t l e v e l v o u t p u t w a v e f o r m ( 4 ) s l e w r a t e = v 0 . 8 t s g 5 a n d s g 6 m u s t c h a n g e c o m p l e t e l y w i t h i n s g 7 l i n t e r v a l . 5 0 % 5 0 % 9 0 % 1 0 % m e a s u r e m e n t l e v e l t m e a s u r e m e n t l e v e l p r o p a g a t i o n d e l a y t i m e t p 5 s
? 10 CXA2504N 1 1 . 5 v 8 v s g 1 0 3 0 s 5 . 5 v 2 v s g 9 5 0 % 5 0 % t r , t f = 1 n s t r , t f = 1 n s 3 0 s o u t p u t w a v e f o r m ( 5 ) 5 0 % m e a s u r e m e n t l e v e l t d
? 11 CXA2504N ( a ) ( s h 4 ) ( b ) s w 1 v 1 ( a ) ( s h 5 ) ( b ) s w 2 v 2 ( a ) ( s h 6 ) ( b ) s w 3 v 3 v 4 ( a ) ( b ) s w 4 ( a ) ( b ) s w 5 v 5 ( a ) ( b ) s w 6 v 6 ( a ) ( b ) s w 7 v 7 ( i n 6 ) ( i n 5 ) ( a ) ( b ) s w 8 v 8 ( i n 4 ) v c c 1 ( a ) ( b ) s w 1 3 v 1 3 ( i n 3 ) ( a ) ( b ) s w 1 4 v 1 4 ( a ) ( b ) s w 1 5 v 1 5 ( i n 2 ) ( a ) ( b ) s w 1 6 v 1 6 ( i n 1 ) t p 1 7 ( a ) ( s h 1 ) ( b ) s w 1 8 v 1 8 ( a ) ( s h 2 ) ( b ) s w 1 9 v 1 9 ( a ) ( s h 3 ) ( b ) s w 2 0 v 2 0 2 5 6 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 3 4 8 9 1 0 7 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 ( a ) ( s h 8 ) ( b ) s w 4 0 v 4 0 t p 3 9 ( a ) ( b ) v 3 8 t p 3 7 ( a ) ( b ) s w 3 6 v 3 6 t p 3 5 ( a ) ( b ) s w 3 4 v 3 4 t p 3 3 v c c 2 s w 3 8 ( a ) ( b ) v 2 8 t p 2 7 s w 2 8 ( a ) ( b ) v 2 6 t p 2 5 s w 2 6 ( a ) ( b ) v 2 4 t p 2 3 s w 2 4 v c c 3 ( a ) ( s h 7 ) ( b ) s w 2 1 v 2 1 1 0 0 . 1 c l c l c l 0 . 1 3 9 0 k 0 . 1 3 9 0 k 0 . 1 3 9 0 k 0 . 1 3 9 0 k 0 . 1 1 0 0 . 1 3 9 0 k 0 . 1 3 9 0 k c l c l c l 4 7 k 0 . 0 1 0 . 1 1 0 0 . 1 3 9 0 k 0 . 1 3 9 0 k 0 . 1 3 9 0 k 3 9 0 k 3 9 0 k 3 9 0 k 3 9 0 k 3 9 0 k 3 9 0 k 0 . 1 3 9 0 k 0 . 1 3 9 0 k 0 . 1 3 9 0 k 2 2 k 0 . 0 1 electrical characteristics measurement circuit
? 12 CXA2504N application circuit 0 . 0 1 4 7 k 3 9 0 k 1 * 1 3 9 0 k 1 * 1 3 9 0 k 1 * 1 3 9 0 k 1 * 1 3 9 0 k 1 * 1 3 9 0 k 1 * 1 c h 6 o u t p u t c h 5 o u t p u t c h 4 o u t p u t 1 5 . 5 v c h 3 o u t p u t c h 2 o u t p u t c h 1 o u t p u t 5 . 0 v r e s a m p l e - a n d - h o l d p u l s e i n p u t r e s a m p l e - a n d - h o l d p u l s e i n p u t * 2 s a m p l e - a n d - h o l d p u l s e i n p u t c h 6 i n p u t c h 5 i n p u t c h 4 i n p u t 0 . 0 1 c h 3 i n p u t c h 2 i n p u t c h 1 i n p u t 1 5 . 5 v 0 . 0 1 2 2 k s a m p l e - a n d - h o l d p u l s e i n p u t 2 5 6 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 1 3 4 8 9 1 0 7 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 * 1 u s e a c e r a m i c c a p a c i t o r w i t h l o w l e a k . * 2 a d j u s t t o c h 1 t o 6 i n p u t s i g n a l d c v o l t a g e ( w i t h i n 1 5 0 m v ) . application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 13 CXA2504N package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r p l a t i n g c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 0 p i n s s o p ( p l a s t i c ) 8 . 4 0 . 4 1 . 4 5 0 . 2 a * 1 3 . 5 0 . 2 0 . 1 0 . 1 0 . 3 0 . 1 * 6 . 3 0 . 2 ( 6 . 9 5 ) ( 1 . 0 5 ) d e t a i l a 0 t o 1 0 0 . 6 5 4 0 2 1 1 2 0 0 . 3 g s s o p - 4 0 p - l 1 1 1 ( 1 . 0 5 ) ( 1 . 0 5 ) 0 . 1 5 0 . 0 5 0 . 1 s s n o t e : * d i m e n s i o n s d o n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 6 5 m 0 . 1 2 s

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